School personnel information

写真b

ITAZAKI Noriyoshi


Organization 【 display / non-display

  • 1998.04.01 - 2005.03.31, Graduate School of Engineering, Research Assistant

  • 2005.04.01 - 2007.03.31, Division of Precision Science & Technology and Applied Physics, Graduate School of Engineering, Research Assistant

  • 2007.04.01 - , Division of Precision Science & Technology and Applied Physics, Graduate School of Engineering, Assistant Professor

Education 【 display / non-display

Hiroshima Institute of Technology Faculty of Engineering  Graduated 1982.04
Hiroshima University Graduate School, Division of Environmental Science  Completed 1986.03
Hiroshima University Graduate School, Division of Engineering  Completed 1989.12

Academic Society Membership 【 display / non-display

  • IEEE

 

Academic Papers 【 display / non-display

  • Built-In Self-Test for Crosstalk Faults in a Digital VLSI, Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita, Systems and Computers in Japan, Vol. 33, no.13, pp.35-47,Vol. 33, no.13, pp.35-47, 2002.11, Papers

  • Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits, Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita, Proc. of 11th Asian Test Symposium, pp.176-181,pp.176-181, 2002.11, International Conference(Proceedings)

  • Reduction of the Target Fault List and fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits, Kazuya Shimizu, Takanori Shirai, Masaya Takamura, Noriyoshi Itazaki, Kozo Kinoshita, IEICE Trans on Information and Systems, Vol. E85-D, no.10, pp.1526-1533,Vol. E85-D, no.10, pp.1526-1533, 2002.10, Papers

  • An Efficient Method of Crosstalk Fault Simulation for Clock Delayed Domino Circuits, Kazuya Shimizu, Takanori Shirai, Masaya Takamura, Noriyoshi Itazaki, Kozo kinoshita, Dig. of European Test Workshop, pp.125-125,pp.125-125, 2002.05, Other

  • Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits, Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita, IEEE International WorkShop on Electronic design, Test and Application, pp.92-96,pp.92-96, 2002.01, Conference Report / Oral Presentation

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