School personnel information

写真b

AWANO Hiromitsu


Keyword

VLSI, Hardware Accelerator, Machine Learning, Hardware Security

URL

https://sites.google.com/site/hiromitsuawano/

Organization 【 display / non-display

  • 2019.01.01 - , Department of Information Systems Engineering, Graduate School of Information Science and Technology, Associate Professor

 

Academic Papers 【 display / non-display

  • BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA, H. Awano,M. Hashimoto, Proceedings of Design, Automation and Test in Europe Conference (DATE), 2020.03, International Conference(Proceedings)

  • An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field., Hiromitsu Awano, Tadayuki Ichihashi, Makoto Ikeda, IEICE Transactions,102-A(1) 56-64, 2019.04, http://search.ieice.org/bin/summary.php?id=e102-a_1_56, Papers

  • Hardware Design of High Precision Discrete Gaussian Sampler for Lattice-based Cryptography,118(273) 13-18, 2018.10, https://ci.nii.ac.jp/naid/40021713365, Conference Report / Oral Presentation (In Japanese)

  • Hardware Design of High Precision Discrete Gaussian Sampler for Lattice-based Cryptography,118(272) 13-18, 2018.10, https://ci.nii.ac.jp/naid/40021713279, Conference Report / Oral Presentation (In Japanese)

  • Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs., Hiromitsu Awano, Takashi Sato, DATE, 1447-1452, 2018.04, https://doi.org/10.23919/DATE.2018.8342239, Papers

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